LDMOS devices and high sheet resistance poly resistors have been widely used in power management and high voltage driver circuit design. As low Rdson is generally preferred for LDMOS devices, N-type LDMOS (LDNMOS) devices have been most commonly used due to their Rdson being lower than P-type LDMOS (LDPMOS) devices since electron mobility is higher than hole mobility. The sheet resistance of the high sheet resistance poly used for the resistors is normally 1 kilo ohm (KΩ)/square (sq) or 2 KΩ/sq and a dedicated mask is used for the poly implant to adjust the resistance. A separate mask is then used for the LDMOS drift region implant and this implant is generally done before the gate oxide layer is formed.
To reduce the Rdson, additional doping has often been applied to the drain side of a substrate to reduce the connection resistance, and it does not degrade the device breakdown voltage as it is far away from the channel. Moreover, to reduce integration costs, standard core device N-wells are often used. However, the disadvantage of using a standard N-well is that low dose shallow threshold voltage (vt) implants are required to meet core PMOS device performance targets, and the low dosage is not helpful to reduce LDNMOS drain resistance. Further, to reduce latchup issues, standard N-well formation normally requires high doping concentrations, e.g., greater than 1e13/centimeter squared (cm2), which generally is too high for LDNMOS drift region doses, e.g., less than 1e13/cm2. In addition, a standard N-well doping profile is not fully optimized for lower Rdson LDNMOS performance. Further, while a dedicated mask for the additional drain implant is helpful for optimizing the LDNMOS Rdson, the necessity of an additional mask is not cost effective.
A need therefore exists for methodology enabling integration of a low Rdson LDNMOS and a high sheet resistance poly resistor, without requiring additional masks, and the resulting device.